With reference to FIG. 1, data is serially transferred on pulse coded modulation (PCM) highway at a frequency common to the two communicating subscriber line audio-processing circuits (SLACs), 12 and 14. The clock that is synchronizing data movement on PCM highway 10 is called a PCM clock (PCLK). A frame synchronization signal (FS) is the reference for the data exchange, FS is synchronized with PCLK. One SLAC will transmit data on the PCM highway when the other reads the PCM highway and vice versa. This transaction of data takes place between each FS. Each FS pulse is a timing reference for a transacting between the two considered SLACs. Each transaction has to be finished before the occurrence of the next FS.
There is an integral number of PCLK between two rising edges of FS. Since eight-bits of data is exchanged between the two SLACs, there must be at least 16 PCLK between two rising edges of FS. During the first 8 PCLKs, there will be a transfer of data in one direction and during the last 8 PCLKs, in the other direction as is illustrated in FIG. 2. The first 8 PCLKs are forming the first time slot 16 and the second 8 PCLKs, the second time slot 18. A PCLK period is called a clock slot. Therefore, there are 8 clock slots in one time slot. In the example, illustrated in FIG. 2 PCLK is 16 times faster than FS, i.e., if FS has a frequency of 8 kHz then PCLK has a frequency of 128 kHz.
In different systems, several channels may be exchanged on the PCM highway. Therefore a larger number of time slots is needed, and PCLK must have a higher frequency. In the case of a Digital Exchange Controller (DEC) such as that manufactured by Advanced Micro Devices, Inc. as part number 79C31, PCLK can go from 64 kHz (one time slot) up to 8.192 MHz (128 time slots). In the case of a SLAC, PCLK can go from 64 kHz to 4.096 Mhz (64 time slots).
All the circuits that have one PCM highway 10 in common must have the same FS and PCLK. Ideally, all the circuits connected to highway 10 are the same and are receiving FS and PCLK at the same time. However, in practice the circuits will have a range of timing characteristics such as the DEC specifications shown in timing diagram of FIG. 3, described in Table 1. With reference to FIG. 3, PCLK 20 and FS 22 are synchronized in such a way that the falling edge 24 of PCLK is to occur when the FS signal is HIGH 26; the duration of the HIGH FS signal is defined by tFSS and tFSH (Table I). A clock slot starts from the time at which PCLK is LOW and ends at the time at which PCLK becomes LOW again. A delay tDXD 28 is incurred before the first data on the PCM highway; the data must be held for time tDXH 30 so that it can catch the falling edge of PCLK 20 in the receiving circuit. The eighth bit is the last one of the slot, so it takes a time tDXZ 32 for the PCM highway to go back to a high-impedance (HI-Z) mode. The timing specifications are similar for a SLAC, although the values are different since the SLAC is a slower circuit.
The problem sought to be addressed by the present invention is the following: The user allocates adjacent time slots for writing on the PCM highway. FIG. 4 illustrates a situation in which the first driver circuit 34 that writes on the PCM highway has relatively slow timing characteristics and the second driver circuit 36 that writes on the PCM highway has relatively fast timing characteristics. The timing specifications in Table I indicate a range of 10 to 70 nsec for both tDXD and tDXZ. Suppose the slow circuit 34 turns off its last bit 38 during 70 nsec, i.e., the output driver turns off 70 nsec after the falling edge of PCLK, and that the fast driver 36 turns on 10 nsec after the falling edge of PCLK in order to transmit the first bit 40. This results in 60 nsec 42 during which both output drivers 34 and 36 attempt to write on the PCM highway. If the drivers attempt to transmit the same data, there is no bus contention; if the drivers attempt to transmit opposite data, the pull-up transistor 43 of one driver will be on as well as the pull-down transistor 44 of the other driver. A large current 45 will be conducted through the two devices and it could damage either or both circuits, probably the fastest one.
TABLE I ______________________________________ PCM Highway Timing Conditions: O &lt; Ta &lt; 70.degree. C., 4.75 v &lt; Vcc &lt;5.25 v, load capacitance on logic outputs (Cl) = 150 pF, 360 ohm pullup on TSCx. Symbol Description Min Type Max Unit ______________________________________ t.sub.PCY PCM Clock Period 0.122 16 us t.sub.PCH PCM Clock High 48 ns Pulse Width t.sub.PCL PCM Clock Low 48 ns Pulse Width t.sub.PCF Fall Time of Clock 5 15 ns t.sub.PCR Rise Time of Clock 5 15 ns t.sub.FSS Frame Sync Setup 25 t.sub.PCY.sup.-30 ns Time t.sub.FSH Frame Sync Hold 20 ns Time t.sub.TSD Delay to TSC Valid 10 70 ns t.sub.TSD Delay to TSC Off 10 60 ns t.sub.DXD PCM Data Output 10 70 ns Delay t.sub.DXH PCM Data Output 10 70 ns Hold Time t.sub.PXZ PCM Data Output 10 70 ns Delay to High Z t.sub.DRB PCM Data Input 25 ns Setup Time T.sub.DRH PCM Data Input 5 ns Hold Time ______________________________________
Now, with reference to FIG. 5, even if both driver circuits 34 and 36 have perfectly identical timing characteristics in that one is writing on the PCM highway just after the other, the system will probably have imperfections so that each driver circuit will detect the falling edge of PCLK at slightly different times; there might be a delay of several nanoseconds due to wire length, distance between boards, etc. So, it is possible that an overlap 46 can be created even if the drivers as shown in FIG. 5 are identical. This could damage the circuits as well.
To avoid that problem, the user could leave one clock slot free 48 as shown in FIG. 6 between two time slots during which two different circuits put data on the bus. This solution, however, imposes an undesired restriction on the user. A circuit capable of eliminating this restriction on the user, and yet avoids bus driver contention, is a more desirable solution.